1. Technical Field
The present invention relates generally to an improved data processing system, and in particular to a method and apparatus for processing data. Still more particularly, the invention relates to a method, apparatus, and algorithm for detecting address match in a deeply pipelined processor design.
2. Description of Related Art
To facilitate debugging of both hardware and software, many processors employ a detector mechanism that can detect an access to a given instruction or data address. A data address is an address that identifies a location of data in memory, including random access memory (RAM), non-volatile memory such as a hard drive, or any other form of memory. Broadly, the detector mechanism is a register that contains the address of interest and a circuit that compares an incoming request for address to the registry to determine whether a match exists. If a match exists, then the program or set of instructions requesting the address may be terminated in order to prevent errors from arising within the program or within the data processing system as a whole, or simply to allow a change of program control. Alternatively, the address match mechanism need not terminate the program. Instead, the address match mechanism may also acknowledge that an address match occurred by setting a bit in a register, or perform a similar action. In either case, the detection of the address match may be used to check the state of the machine, check the program data, or verify some other aspect of the hardware, the set of instructions executed, data related to the process, or other aspects of the data processing system.
For processors managing large address ranges, such as 64-bit addresses, the straightforward approach of comparing every bit is impracticable when the cycle time is reduced, especially in highly pipelined processors. The many levels of gates needed to perform the comparison use an unacceptably long processor cycle time. Furthermore, the many levels of gates needed require an unacceptably large amount of physical space on the processor chip. Thus, a comparator circuit is needed that both reduces the amount of time within a cycle that is needed to perform a match check and occupies a small area on the processor chip.
The problem of designing a comparator system to perform match checking is exacerbated by the fact that the comparator system should be physically located in the area of the critical timing path of the processor. This location is preferred because the input to the comparator is the address that is to be accessed by the processor, and because the address is likely to lie on the critical timing path.
Because the comparator circuit should be located in a critical physical area of the processor chip and because many other circuits benefit from being physically placed in the critical area, the physical area used by the comparator circuit should be as small as possible. Furthermore, the problem of designing the comparator system is further exacerbated in multi-threaded designs where a unique address of interest exists for each thread. Thus, a great number of register values are held for comparison. Accordingly, it would be advantageous to have an improved method, apparatus, and algorithm for reducing the amount of time within a processor cycle needed to perform a match check.